1. Field of the Invention
The present invention relates to a memory controller, and particularly relates to an output signal driving circuit of the memory controller.
2. Description of the Prior Art
As CPU performance has greatly improved in recent years, memory bandwidth has become a serious restriction to a computer system's performance. Therefore, semiconductor and chip manufacturers have developed new memory standards and bus techniques to solve the memory bandwidth problem. For example, a memory standard known as DDR (Double data rate) has been developed, which comprises DDRI, DDRII standard, and the newest DDRIII standard.
However, while new memory interfacing standards can greatly increase memory data access amount, semiconductor manufacturers such as TSMC and UMC are having difficulty providing optimal ASIC (Application Specific Integrated Circuit) manufacturing processes that can make the most use out of these new memory standards. According to the DDR standard by JDEC, DDRI type memory conforms to the SSTL-25 standard, which prescribes an I/O port voltage of 2.5V; DDRII type memory conforms to the SSTL-18 standard, which prescribes an I/O port voltage of 1.8V; and DDRIII type memory conforms to the SSTL-15 standard, which prescribes an I/O port voltage of 1.5V.
That being the case, the ASIC process provided by the semiconductor manufacturers normally only distinguishes between two types of device: low voltage devices and high voltage devices. It should be noted that the major difference between the high voltage device and the low voltage device is the thickness of their gate oxide. The high voltage device has a thicker gate oxide layer than the low voltage device, and one major function of the high voltage device is to be applied in I/O circuitry. Taking a widely seen standard CMOS process as an example, for a 0.25 um, 0.18 um, 0.13 um, or even smaller-size process, the high voltage device is usually nominally applied with a supply voltage of 3.3V.
Generally speaking, conventionally when designing an output signal driving circuit of a memory controller, PMOS transistors are used as voltage pull-up device and NMOS transistors are used as voltage pull-down device, such that a voltage value on an I/O pad can be pulled up/down according to the operation of the memory controller. However, as described above, because a high-voltage device commonly used for I/O circuitry is optimally operable under a power supply voltage of 3.3V, if such a memory device is to be operated in conformity with DDRI (2.5V), DDRII (1.8V), or DDRIIII (1.5V) standard, the operation voltage becomes insufficiently large for the voltage pull-up device implemented by a PMOS transistor. In this case, the size of the PMOS transistor is usually increased, i.e., the device width increased, such that the ability for draining current of the PMOS transistor can be enhanced. Such a structural change will significantly increase the area of the I/O pad.